1. Field of the Invention
The present invention relates to an A/D (analog-digital) converter in which one or more analog voltages to be converted are sampled and held and the sampled and held one or more analog voltages to be converted are compared with a reference voltage given by a voltage change value of a ramp voltage having a voltage value changing monotonically for a certain period or a voltage proportional to the voltage change value, and each of the one or more analog voltages to be converted is converted to a digital value corresponding to the reference voltage and outputted, and more particularly, to a column-type A/D converter.
2. Description of the Related Art
Recently, high speed and low power consumption are increasingly demanded in a A/D converter used in a solid-state image sensor. In order to satisfy the above demand, a column-type A/D converter is used in many cases (refer to Japanese Unexamined Patent Publication No. 2000-286706).
FIG. 1 is a block diagram showing a conventional column-type A/D converter. A column-type A/D converter 11 comprises an inverter circuit 12, a switch RS to short-circuit an input node CPI and an output node CPO of the inverter circuit 12, a capacitor CS to sample an analog voltage to be converted, a capacitor CR and a switch S3 to transmit a ramp voltage VRAMP changing its voltage value monotonically for a certain period, to the input node CPI, a switch SS to sample the analog voltage to be converted, and a latch circuit 13 to latch a counter output corresponding to the analog voltage to be converted as circuit elements. Furthermore, in FIG. 1, a ramp voltage source 14 to generate the ramp voltage VRAMP, a counter 15 to count and output a digital value (n-bit binary signal) corresponding to the voltage value change of the ramp voltage, and a pixel part 16 of a solid-state image sensor for the column-type A/D converter 11 are illustrated.
The A/D conversion operation of the column-type A/D converter 11 will be described with reference to a timing chart shown in FIG. 2.
At a timing t1, when a switch RX of the pixel part 16 is turned on, a node FD is reset to a voltage VDD, a node VIN is charged to a high potential through a MOS transistor MA. In addition, the switch RS is turned on at the same time, and the input node CPI and the output node CPO of the inverter circuit 12 are short-circuited and the input node CPI is automatically reset to an input determination voltage (auto-zero level) of the inverter circuit 12. Although the switch SS is turned on at the same time, switches S3 and TX are in off state.
At a timing t2, when the switch RX is turned off, a reset voltage appears at the node VIN. At a timing t3, when the switch RS is turned off, a reset voltage is sampled in the capacitor CS.
Then, at a timing t4, when the switch Tx is turned on, a photoelectric conversion is performed by a photoelectric conversion element (photodiode) PD of the pixel part 16 and accumulated electric charge is transferred to the node FD, so that the node VIN is shifted to a voltage level (photoelectric conversion level) corresponding to the photoelectric-converted electric charge amount. When the voltage level of the node VIN is stabilized at a timing t5 and the switch Tx is turned off and the switch S3 is turned on, a voltage difference between the voltage level (photoelectric conversion level) of the node VIN at that time and an initial voltage of the ramp voltage VRAMP is held in the capacitor CR.
Sequentially, at a timing t6, when the switch SS is turned off, a differential value VSIG between the reset voltage (timing t3) and the photoelectric conversion level (timing t6) of the node VIN is held in the input node CPI as an analog voltage to be converted.
At a timing t7, when a voltage value of the ramp voltage VRAMP starts to increase gradually, the voltage of the input node CPI is also increased so as to be proportional to the voltage increase of the ramp voltage VRAMP. In addition, at the timing t7, the counter 15 starts to count at the same time.
At a timing t8, when the voltage level of the input node CPI exceeds the input determination voltage of the inverter circuit 12, the inverter circuit 12 inverts the output level of the output node CPO. The latch circuit 13 holds the value of the counter output in response to output change of the output node CPO.
Here, the differential value VSIG corresponds to an incident light amount to the photoelectric conversion element PD, and the value of the latched counter output is equal to an A/D conversion value (digital value) of the differential VSIG. Thus, when the A/D conversion value held by the latch circuit 13 is outputted, the column-type A/D converter 11 completes the A/D conversion operation of the analog voltage VSIG to be converted.
FIG. 3 shows input/output characteristics of the inverter circuit 12 that compares the analog voltage VSIG to be converted with the voltage increased value of the ramp voltage VRAMP, in the column-type A/D converter 11. The inverter circuit 12 executes the voltage comparison by comparing the difference voltage between the analog voltage VSIG to be converted and the voltage increased value of the ramp voltage VRAMP as an input voltage, with the auto-zero level of the input determination voltage.
The auto-zero level is a voltage provided when the input and output of the inverter circuit 12 are short-circuited, and the voltage is at an intersection of an input/output characteristic curve A of the inverter with a straight line B in which the input voltage Vin equals the output voltage Vout (Vin=Vout).
When it is assumed that the threshold values of the P channel-type MOSFET and the N channel-type MOSFET in the inverter circuit 12 are Vthp and Vthn, respectively and their transfer conductance are βp and βn, since the current amounts flowing through both MOSFETs of the inverter circuit 12 are equal, the following formula 1 is provided. In addition, in the formula 1, VDD is a power supply voltage supplied to the source terminal of the P channel-type MOSFET, and VX is an auto-zero level and VX is expressed by the formula 2.βn/2×(Vx−Vthn)2=βp/2×(VDD−Vx−Vthp)2  (1)Vx=Vin=Vout  (2)
When the equation of the formula 1 is solved for Vx, the auto-zero level Vx is expressed by the following formula 3.Vx={(βn/βp)1/2×Vthn+VDD−Vthp}/(1+(βn/βp)1/2)  (3)
It can be understood from the formula 3 that the voltage fluctuation of the auto-zero level Vx is proportional to the voltage fluctuation of the power supply voltage VDD.
FIG. 4 shows input/output characteristics of the inverter circuit when the power supply voltage VDD fluctuates. As schematically shown in FIG. 4, when the power supply voltage VDD fluctuates by a voltage A, the auto-zero level Vx shifts from Vx1 to Vx2.
The influence of the power supply voltage fluctuation on the latch output (counter output value held in and outputted from the latch circuit 13) will be described with reference to a timing chart shown in FIG. 5.
When the power supply voltage VDD fluctuates only by the voltage Δ during the A/D conversion operation, since the auto-zero level shifts from Vx1 to Vx2, the falling timing of the output node CPO of the inverter circuit shifts from t8 to t9. That is, the latch output value is changed because the timing to latch the counter output is delayed. Such influence due to the power supply voltage fluctuation causes the fluctuation of the A/D conversion output directly. Therefore, the digital image from the solid-state image sensor is superimposed with a noise according to the power supply voltage fluctuation.